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TB62214AFG/aftg 2012-03-12 1 toshiba bicd integrated circuit silicon monolithic TB62214AFG, tb62214aftg bicd constant-current two-phase bipolar stepping motor driver ic the TB62214AFG/aftg is a two-phase bipolar stepping motor driver using a pwm chopper controlled by clock input. fabricated with the bicd process, the TB62214AFG/aftg is rated at 40 v/2.0 a . the on-chip voltage regulator allows control of a stepping motor with a single v m power supply. features ? bipolar stepping motor driver ? pwm constant-current drive ? clock input control ? allows two-phase, 1-2-phase and w1-2-phase excitations. ? bicd process: uses dmos fets as output power transistors. ? high voltage and current: 40 v/2.0 a (absolute maximum ratings ? thermal shutdown (tsd), over current shutdown (isd), and power-on-resets (pors) ? packages: hsop28-p-0450-0.80 qfn48-p-0707-0.50 TB62214AFG hsop28-p-0450-0.80 tb62214aftg qfn48-p-0707-0.50 weight hsop28-p-0450-0.80 : 0.79 g (typ.) qfn48-p-0707-0.50 : 0.14 g (typ.)
TB62214AFG/aftg 2012-03-12 2 pin assignment TB62214AFG (hsop28) oscm vref_a 1 cw/ccw out_a reset rs_a out_a cl k d_mode_1 mo_out d_mode_2 2 3 4 5 6 7 8 9 10 11 14 12 13 21 15 16 17 18 19 20 22 23 24 25 26 27 28 enable fin(gnd) nc nc gnd gnd vref_b nc vcc v m fin(gnd) nc nc nc rs_b out_b gnd gnd out_b
TB62214AFG/aftg 2012-03-12 3 pin assignment tb62214aftg ( qfn48 ) *mark pad: it must be connected to gnd 1 2 3 4 5 6 7 8 9 10 11 12 36 nc out_b1 35 34 33 32 31 30 29 28 27 26 25 out_b2 nc nc rs_b2 rs_b1 nc v m nc nc v cc 37 nc out_a2 out_a1 nc rs_a2 rs_a1 nc gnd enable clk nc 38 nc nc 39 nc 40 gnd 41 v ref_b 42 v ref_a 43 oscm 44 cw/ccw 45 mo_out 46 d_mode_1 47 d_mode_2 48 nc 24 nc 23 nc 22 gnd 21 out_b1 20 19 gnd 18 gnd 17 out_a2 16 out_a1 out_b2 15 gnd 14 nc 13 nc reset * * * *
TB62214AFG/aftg 2012-03-12 4 block diagram in the block diagram, part of the fu nctional blocks or constants may be omitted or simplified for explanatory purposes. note: all the grounding wires of the TB62214AFG/aftg must r un on the solder mask on the pcb and be externally terminated at only one po int. also, a grounding method should be considered for efficient heat dissipation. careful attention should be paid to the layout of the output, v dd (v m ) and gnd traces, to avoid short-circuits across output pins or to the power supply or ground. if such a short-circuit occurs, the TB62214AFG/aftg may be permanently damaged. also, utmost care should be taken for pattern designing and implementation of the TB62214AFG/aftg since it has the power supply pins (v m , rs _ a, rs_b, out_a, out_a , out_b, out_b , gnd) particularly a large current can run through. if these pins are wired incorrectly, an operation error or even worse a destruction of the TB62214AFG/aftg may occur. the logic input pins must be correctly wired, too; otherwise, the TB62214AFG/aftg may be damaged due to a current larger than the specifie d current running through the ic. please note the above when design ing and implementing ic patterns. detection circuit current feedback (2) chopper osc reset cw/ccw enable d_mode_1 d_mode_2 clk current level set vcc voltage regulator osc cr-clk converter oscm vcc vref v rs vmr detect vm rs r s comp output control (mixed decay control) vm vmr detect tsd isd output (h-bridge2) stepping motor enable vm mo_out step decoder (input logic)
TB62214AFG/aftg 2012-03-12 5 pin function TB62214AFG (hsop28) pin no. pin name function 1 cw/ccw motor rotation: forward/reverse 2 mo_out electric angle monitor 3 d_mode_1 excitation mode control 4 d_mode_2 excitation mode control 5 clk an electrical angle leads on the rising edge of the clock input. a motor rotation count depends on the input frequency. 6 enable a-/b-channel output enable 7 reset electric angle reset 8 rs_a the sink current sensing of a-phase motor coil 9 nc no-connect 10 out_a a-phase positive driver output 11 nc no-connect 12 gnd motor power ground 13 out_a a-phase negative driver output 14 gnd motor power ground 15 gnd motor power ground 16 out_b b-phase negative driver output 17 gnd motor power ground 18 nc no-connect 19 out_b b-phase positive driver output 20 nc no-connect 21 rs_b the sink current sensing of b-phase motor coil 22 v m power supply 23 v cc smoothing filter for logic power supply 24 nc no-connect 25 nc no-connect 26 v ref_b tunes the current level for b-phase motor drive. 27 v ref_a tunes the current level for a-phase motor drive. 28 oscm oscillator pin for pwm chopper pin interfaces (hsop28) the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. absolute precision of the chip internal resistance is +/-30%. 1 100k ? 3 150 ? 4 5 fin 6 7 28 1k ? 500 ? fin 26 27 23 fin 1k ? 22 8k ? 3k ? 3k ? 14 8 12 10 13 19 16 15 17 21 2 fin 150 ? 100k ?
TB62214AFG/aftg 2012-03-12 6 tb62214aftg (qfn48) pin no. pin name function pin no. pin name function 1 nc no-connect 25 nc no-connect 2 clk an electrical angle leads on the rising edge of the clock input. a motor rotation count depends on the input frequency. 26 out_b2 3 enable a-/b-channel output enable 27 out_b1 b-phase positive driver output 4 reset electric angle reset 28 nc no-connect 5 gnd logic ground 29 rs_b2 6 nc no-connect 30 rs_b1 power supply of b-phase motor coil and the sink current sensing of b-phase motor coil 7 rs_a1 31 nc no-connect 8 rs_a2 power supply of a-phase motor coil and the sink current sensing of a-phase motor coil 32 v m power supply 9 nc no-connect 33 nc no-connect 10 out_a1 34 v cc smoothing filter for logic power supply 11 out_a2 a-phase positive driver output 35 nc no-connect 12 nc no-connect 36 nc no-connect 13 nc no-connect 37 nc no-connect 14 nc no-connect 38 nc no-connect 15 gnd motor power ground 39 nc no-connect 16 out_a1 40 gnd logic ground 17 out_a2 a-phase negative driver output 41 v ref_b tunes the current level for b-phase motor drive. 18 gnd motor power ground 42 v ref_a tunes the current level for a-phase motor drive. 19 gnd motor power ground 43 oscm oscillator pin for pwm chopper 20 out_b2 44 cw/ccw motor rotation: forward/reverse 21 out_b1 b-phase negative driver output 45 mo_out electric angle monitor 22 gnd motor power ground 46 d_mode_1 excitation mode control 23 nc no-connect 47 d_mode_2 excitation mode control 24 nc no-connect 48 nc no-connect pin interfaces (qfn48) the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. absolute precision of the chip internal resistance is +/-30%. 43 1k ? 500 ? 40 3 44 2 100k ? 150 ? 4 40 46 47 41 1k ? 42 34 40 7 32 8k ? 3k ? 3k ? 30 18 8 15 10 11 16 17 27 21 26 20 19 22 29 45 40 150 ? 100k ?
TB62214AFG/aftg 2012-03-12 7 clk function the electrical angle leads one by one in the manner of the clocks. the cloc k signal is reflected to the electrical angle on the rising edge. clk input function rise the electrical angle leads by one on the rising edge. fall remains at the same position. enable function the enable pin controls whether or not to let the current flow through a given phase for a stepper motor drive. this pin serves to select if the motor is stopped in off mode or activated. the pin must be fixed to low on the power-on or power-down of the TB62214AFG/aftg. during power on, once the vm voltage has reached the voltage required to operate the motor, set this to high. enable input function h output transistors are enabled (normal operation mode). l output transistors are disabled (high impedance state). cw/ccw function the cw/ccw pin switches rotation direction of stepper motors. the cw pin outputs the a-phase current 90 behind than the b-phase current. the ccw pin outputs the a-phase curre nt 90 ahead of the b-phase current. cw/ccw input function h forward (cw) l reverse (ccw) excitation mode select function d_mode_1 d_mode_2 function l l osc_m, output transistors are disabled (in standby mode) l h two-phase excitation h l 1-2-phase excitation h h w1-2-phase excitation reset function the reset function resets the electric al angle. always set this to h during power on. once the vm voltage has reached the voltage required to operate the motor, release reset. reset input function l normal operation mode h the electrical angle is reset. the phase current while reset is applied is shown in the table below. mo_out is low at this time. excitation mode a-phase current b-phase current 2 phase 100% 100% 1 ? 2 phase 100% 100% w1-2 phase 71% 71%
TB62214AFG/aftg 2012-03-12 8 detection features (1) thermal shutdown (tsd) the thermal shutdown circuit turns off all th e outputs when the ju nction temperature (t j ) exceeds 150c (typ.). the outputs retain the current states. the TB62214AFG/aftg exits tsd mode and resume normal operation when the TB62214AFG/aftg is rebooted or both the d_mode_1 and d_ mode_2 pins are switched to low. (2) power-on-resets (pors) for v mr and v ccr (v m and v cc voltage monitor) the outputs are forced off until v m and v cc reach the rated voltages. (3) overcurrent shutdown (isd) each phase has an overcu rrent shutdown circuit, which turns off the corresponding outputs when the output current exceeds the shutdown trip threshold (above the maximum current rating: 2.0 a minimum). the TB62214AFG/aftg exits isd mode and resumes normal operation when the TB62214AFG/aftg is rebooted or both the d_mode_1 and d_ mode_2 pins are switched to low. this circuit provides protection ag ainst a short-circuit by temporarily disabling the device. important notes on this feature will be provided later.
TB62214AFG/aftg 2012-03-12 9 absolute maximum ratings (ta = 25c) characteristics symbol rating unit remarks motor power supply v m 40 v ? motor output voltage v out 40 v ? motor output current i out 2.0 a per phase (note 1) digital input voltage v in -0.5 to 6.0 v ? vref standard voltage v ref 5.0 v ? mo output voltage v mo 6.0 v ? mo output sink current i mo 30.0 ma ? qfn48 p d 1.3 w (note 2) power dissipation hsop28 p d 1.3 w (note 2) operating temperature t opr ? 20 to 85 c ? storage temperature t stg ? 55 to 150 c ? junction temperature t j (max) 150 c ? note 1: as a guide, the maximum output current should be kept below 1.4 a per phase. the maximum output current may be further limited by thermal considerations, dep ending on ambient temperature and board conditions. note 2: stand-alone (ta = 25c) if ta is over 25c, derating is required at 10.4 mw/c. ta: ambient temperature t opr : ambient temperature while the TB62214AFG/aftg is active t j : junction temperature while the TB62214AFG/aftg is active. the maximum junction temperature is limited by the thermal shutdown (tsd) circuitry. it is advisable to keep the maximum current below a certain level so that the ma ximum junction temperature, t j (max) , will not exceed 120c. note: the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating (s) may cause breakdown, damage or deter ioration of the device, and may result in injury by explosion or combustion. the value of even one parameter of the absolute maximum ratings should not be exceeded under any circumstances. the TB62214AFG/aftg does not have overvoltage protecti on. therefore, the devic e is damaged if a voltage exceeding its rated maximum is applied. all voltage ratings including supply voltages must always be followed. the other notes and considerations described later should also be referred to. operating ranges (ta=0 to 85 c) characteristics symbol min typ. max unit remarks motor power supply v m 10.0 24.0 38.0 v ? motor output current i out ? 1.4 2.0 a per phase (note 1) v in (h) 2.0 ? 5.5 v high-level logic digital input voltage v in (l) -0.4 ? 1.0 v low-level logic mo output voltage v mo ? 3.3 5.5 v with a pull-up resistor clock input frequency f clk ? ? 100 khz ? chopper frequency f chop 40.0 100.0 150 khz ? v ref reference voltage v ref gnd ? 3.6 v ? voltage across the current-sensing resistor pins v rs 0.0 1.0 1.5 v referenced to the v m pin (note 2) note 1: the actual maximum current may be limited by the operating environment (operating conditions such as excitation mode or operating duration, or by the surrounding temperature or board heat dissipation). determine a realistic maximum current by calculating the heat generated under the operating environment. note 2: the maximum v rs voltage should not exceed the maximum rated voltage.
TB62214AFG/aftg 2012-03-12 10 electrical characteristics 1 (ta = 25c, v m = 24 v, unless otherwise specified) characteristics symbol te s t circuit test condition min typ. max unit input hysteresis voltage v in (his) dc digital input pins (note) 100 200 300 mv high i in (h) dc v in = 5 v at the digital input pins under test 35 50 75 a digital input current low i in (l) dc v in = 0 v at the digital input pins under test ? ? 1 a high v oh (mo) ? i oh = 24 ma when the output is high 2.4 ? ? v mo output voltage low v ol (mo) ? i ol = 24 ma when the output is low ? ? 0.5 v i m1 dc outputs open, in standby mode ? ? 3 ma i m 2 dc outputs open, enable = low ? 3.5 5 ma supply current i m3 dc outputs open (two-phase excitation) ? 5 7 ma high-side i oh dc v rs = v m = 40 v, v out = 0 v ? ? 1 a output leakage current low-side i ol dc v rs = v m = v out = 40 v 1 ? ? a channel-to-channel differential i out1 dc channel-to-channel error ? 5 0 5 % output current error relative to the predetermined value i out2 dc i out = 1 a ? 5 0 5 % rs pin current i rs dc v rs = v m = 24 v 0 ? 10 a drain-source on-resistance of the output transistors (upper and lower sum) r on (d-s) dc i out = 2.0 a, t j = 25c ? 1.0 1.5 note: v in (l h) is defined as the v in voltage that causes the outputs (out_a1, out_a2, out_b1 and out_b2) to change when a pin under test is gradually raised from 0 v. v in (h l) is defined as the v in voltage that causes the outputs (out_a1, out_a2, out_b1 and ou t_b2) to change when the pin is then gradually lowered. the difference between v in (l h) and v in (h l) is defined as the input hysteresis.
TB62214AFG/aftg 2012-03-12 11 electrical characteristics 2 (ta = 25c, v m = 24 v, unless otherwise specified) characteristics symbol te s t circuit test condition min typ. max unit v ref input current i ref dc v ref = 3.0 v ? 0 1 a v ref decay rate v ref (gain) dc v ref = 2.0 v 1/4.8 1/5.0 1/5.2 ? tsd threshold (note 1) t j tsd dc ? 140 150 170 c v m recovery voltage v mr dc ? 7.0 8.0 9.0 v overcurrent trip threshold (note 2) isd dc ? 2.0 3.0 4.0 a supply voltage for internal circuitry v cc dc i cc = 5.0 ma 4.75 5.00 5.25 v note 1: thermal shutdown (tsd) circuitry when the junction temperature of the dev ice has reached the threshold, the tsd circuitry is tripped, causing the internal reset ci rcuitry to turn off the output transistors. the tsd circuitry is tripped at a temperature between 140c (min) and 170c (max). once tripped, the tsd circuitry keeps the output transist ors off until both the d_mode_1 and d_ mode_2 pins are switched to low or the TB62214AFG/aftg is rebooted. the thermal shutdown circuit is provided to turn off all the outputs when the ic is overheated. for this reason, please avoid using tsd for other purposes. note 2: overcurrent shutdown (isd) circuitry when the output current has reached the threshold, the isd circuitry is tripped, causing the internal reset circuitry to turn off the output transistors. to prevent the isd circuitry from being tripped due to switching noise, it has a masking time of four cr oscillator cycles. once tripped, it takes a maximum of four cycles to exit isd mode and resume normal operation. the isd circuitry remains active until both the d_mode_1 and d_mode_2 pins are switched to low or the TB62214AFG/aftg is rebooted. the TB62214AFG/aftg remains in standby mode while in isd mode. note 3: if the supply voltage for internal circuitry (v cc ) is split with an external resistor and used as v ref input supply voltage, the accuracy of the output current setting will be at 8% when the v cc output voltage accuracy and the v ref damping ratio accuracy are combined. note 4: the circuit design has been designed so that electr omotive force or leak current from signal input does not occur when vm voltage is not supplied, even if the logi c input signal is input. even so, regulate logic input signals before resupply of vm voltage so that t he motor does not operate when voltage is reapplied. back-emf while a motor is rotating, there is a timing at which po wer is fed back to the power supply. at that timing, the motor current recirculates back to the power su pply due to the effect of the motor back-emf. if the power supply does not have enough sink capability , the power supply and output pins of the device might rise above the rated voltages. the magnitude of the mo tor back-emf varies with usage conditions and motor characteristics. it must be fully veri fied that there is no risk that the TB62214AFG/aftg or other components will be damaged or fail due to the motor back-emf. cautions on overcurrent shutdown (isd) and thermal shutdown (tsd) the isd and tsd circuits are on ly intended to provide temporary protection against irregular conditions such as an output short-circuit; they do not necessa rily guarantee the complete ic safety. if the device is used beyond the specified operating ranges , these circuits may not operat e properly: then the device may be damaged due to an output short-circuit. the isd circuit is only intended to provide a temporary protec tion against an output short-circuit. if such a condition persists for a long time, the device may be da maged due to overstress. over current conditions must be removed immediately by external hardware. ic mounting do not insert devices incorrectly or in the wrong orientat ion. otherwise, it may caus e breakdown, damage and/or deterioration of the device.
TB62214AFG/aftg 2012-03-12 12 ac electrical characteristics (ta = 25c, v m = 24, 6.8 mh/5.7 ) characteristics symbol te s t circuit test condition min typ. max unit clock input frequency f clk ac f osc = 1600 khz ? ? 100 khz minimum high pulse width of clk input filter t clk (h) ac high time of the clock input frequency 300 ? ? ns minimum low pulse width of clk input filter t clk (l) ac low time of the clock input frequency 250 ? ? ns t r ac ? 100 150 200 ns t f ac ? 100 150 200 ns t plh (clk) ac clk to out ? 1000 ? ns output transistor switching characteristics t phl (clk) ac clk to out ? 1500 ? ns blanking time for current spike prevention t blank ac i out =1.0 a 200 300 500 ns osc_m oscillation frequency f osc ac c osc = 270 pf, r osc = 3.6 k 1200 1600 2000 khz chopper frequency range f chop(range) ac v m =24v, output active (l out =1.0a) 40 100 150 khz chopper setting frequency f chop ac output active (l out =1.0a) ? 100 ? khz isd masking time t isd (mask) ac after isd threshold is exceeded due to an output short-circuit to power or ground ? 4 ? cr-clk isd on-time t isd ac after isd threshold is exceeded due to an output short-circuit to power or ground 4 ? 8 cr-clk timing charts of output transistors switching timing charts may be simplified for explanatory purposes. 90% 50% 10% 10% 50% 90% 50% 90% 50% 10% 1/f clk t plh t phl t r v m gnd output voltage clk t f
TB62214AFG/aftg 2012-03-12 13 z current waveform in mixed-decay mode timing charts may be simplified for explanatory purposes. mixed-decay mode, the purpose of which is constant-current control, starts out in fast-decay mode for 37.5% of the whole period and then is followed by sl ow-decay mode for the remainder of the period. z timing charts of clk, output current and mo output timing charts may be simplified for explanatory purposes. a phase b phase mo output a phase b phase mo output a phase b phase mo output clock input 1-2-phase excitation w1-2 phase excitation two-phase excitation mdt (mixed decay timing) point: 37.5% (6/16) fixed internal cr clk nf nf i out f chop f chop mdt mdt predefined current level 37.5% mixed-decay predefined current level
TB62214AFG/aftg 2012-03-12 14 z current waveform in mixed (slow + fast) decay mode timing charts may be simplified for explanatory purposes. when a current value increases (mix ed-decay point is fixed to 37.5%) when a current value decreases (mix ed-decay point is fixed to 37.5%) the charge period starts as the internal oscillator cloc k starts counting. when the output current reaches the predefined current level, the internal rs comparator detects the predefin ed current level (nf); as a result, the ic enters slow-decay mode. the TB62214AFG/aftg transits from slow-decay mode to fast-decay mode at the point 37.5 of a pwm frequency (one chopping frequency) remains in a whole pwm frequency period (on the rising edge of the 11th clock of the oscm clock). when the oscm pin clock counter cl ocks 16 times, the fast-decay mode ends; and at the same time, the counter is reset, which brings the tb 62214afg/aftg into charge mode again. note: these figures are intended for illustrative purposes only. if designed more realistically, they would show transient response curves. internal oscm clk predefined current level f chop f chop f chop f chop nf nf nf nf charge slow slow charge fast fast charge slow fast slow charge fast predefined current level nf nf internal oscm clk predefined current level charge f chop f chop f chop f chop nf predefined cur r ent level charge slo w slo w charge fast fast nf nf slow fast slow charge fast the ic enters charge mode for a moment at which the internal rs comparator compares the values. the ic immediately enters slow-decay mode because of the current value exceedin g the charge
TB62214AFG/aftg 2012-03-12 15 z output transistor operating modes output transistor operating modes clk u1 u2 l1 l2 charge on off off on slow-decay mode off off on on fast-decay mode off on on off note: this table shows an example of when the current flows as indicated by the arrows in the figures shown above. if the current flows in the opposite direction, refer to the following table. clk u1 u2 l1 l2 charge off on on off slow-decay mode off off on on fast-decay mode on off off on the TB62214AFG/afgt switches amon g charge, slow-decay and fast-decay modes automatically for constant-current control. the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. calculation of the predefined output current for pwm constant-current control, the TB62214AFG/aftg us es a clock generated by the cr oscillator. the peak output current can be set via the current-sensing resistor (r rs ) and the reference voltage (v ref ), as follows: i out = v ref /5 rs ( ) where, 1/5 is the v ref decay rate, v ref (gain) . for the value of v ref (gain) , see the electrical characteristics table. for example, when vref = 3 v, to generate an output current (i out ) of 0.8 a, r rs is calculated as: r rs = (v ref /5) i out = (3/5) 0.8 = 0.75 . ( 0.5 w) u1 l1 u2 l2 off off u1 l1 u2 l2 off on on load u1 l1 u2 l2 load pgnd r s pin r rs v m on on load charge mode a current flows into the motor coil. slow-decay mode a current circulates around the motor coil and this device. fast-decay mode the energy of the motor coil is fed back to the power on r s pin r s pin off off on off v m v m r rs r rs pgnd pgnd
TB62214AFG/aftg 2012-03-12 16 ic power consumption the power consumed by the tb62214af g/aftg is approximately the sum of the following two: 1) the power consumed by the output transistor s, and 2) the power consumed by the digital logic and pre-drivers. the power consumed by the output tr ansistors is calculated, using the r on (d-s) value of 1.0 . whether in charge, fast decay or slow decay mode, tw o of the four transistors comprising each h-bridge contribute to its power co nsumption at a given time. thus the power consumed by each h-bridge is given by: p (out) = i out (a) v ds (v) = 2 i out 2 r on ......................................... (1) in two-phase excitation mode (i n which two phases have a phase difference of 90), the average power consumption in the output tran sistors is calculated as follows: r on = 1.0 (@2.0 a), the sum of the high-side dmos and low-side dmos i out (peak) = 1.0 a v m = 24 v p (out) = 2hsw 1.0 2 (a) 1.0 ( ) = 2.0 (w )................................................ (2) the power consumption in the i m domain is calculated separa tely for normal operation and standby modes: normal operation mode: i (i m3 ) = 5.0 ma (typ.) standby mode: i (i m1 ) = 2.0 ma (typ.) the current consumed in the digital logic portion of the TB62214AFG/aftg is indicated as i mx . the digital logic operates off a voltage regula tor that is internally connected to the v m power supply. it consists of the digital logic connected to v m (24 v) and the network affect ed by the switching of the output transistors. the total power consumed by i mx can be estimated as: p (i m ) = 24 (v) 0.005 (a) = 0.12 (w )........................................................... (3) hence, the total power consumption of the TB62214AFG/aftg is: p = p (out) + p (i m ) = 2.12 (w) the standby power consumption is given by: p (standby) + p (out) = 24 (v) 0.002 (a) = 0.048 (w) board design should be fully verified, taki ng thermal dissipation into consideration.
TB62214AFG/aftg 2012-03-12 17 z osc-charge delay timing charts may be simplified for explanatory purposes. since the rising level of the osc waveform is referenc ed to convert it into the internal cr clk waveform, about up to1 us (when cr = 1600 khz) of a delay occurs between the osc waveform and internal cr clk waveform. timing waveforms of osc and internal cr clk t chop osc charge delay h l predefined current level osc fast delay osc (cr) 50% 50% l h h l l charge 50% slow fast output voltage out_a output voltage a_out output current internal cr clk
TB62214AFG/aftg 2012-03-12 18 phase sequences two-phase excitation mode 1-2-phase excitation mode w1-2-phase excitation mode ? 150 ? 100 ? 50 50 100 150 0 ? 150 ? 100 ? 50 50 100 150 0 b phase a phase ccw cw initialize position mo output: low ? 150 ? 100 ? 50 50 100 150 0 ? 150 ? 100 ? 50 50 100 150 0 b phase a phase ccw cw initialize position mo output: low a phase ? 150 ? 100 ? 50 50 100 150 0 ? 150 ? 100 ? 50 50 100 150 0 b phase ccw cw initialize position mo output: low
TB62214AFG/aftg 2012-03-12 19 overcurrent shutdown (isd) circuitry isd masking time and isd on-time the overcurrent shutdown (isd) circuitry has a masking time to prevent current spikes during irr and switching from erroneously tripping the isd circuitr y. the masking time is a function of the chopper frequency obtained by cr: masking_time = 4 cr_frequency the minimum and maximum times taken to turn off the output transistor s since an overcu rrent flows into them are: min: 4 cr_frequency max: 8 cr_frequency it should be noted that these values assume a case in which an overcurren t condition is detected in an ideal manner. the isd circuitry might not work, depending on the control timing of the output transistors. therefore, a protection fuse must always be added to the vm power supply as a safety precaution. the optimal fuse capacitance va ries with usage conditions, and one that does not adversely affect the motor operation or exceed the power dissipation rati ng of the TB62214AFG/aftg should be selected. calculating oscm oscillating frequency the oscm oscillating frequency can be ap proximated using the following equation: where: c = capacitor capacity r1= resistance assigning c = 270 10 ? 12 [f], r1= 3600 [ ? ] to get: f oscm = 1.61 10 6 ? 1.6 mhz osc_m oscillation (chopper waveform) a n overcurrent starts flowing into the output transistors disabled (reset state) isd masking time min max min max 1 chopping cycle isd on-time )r(c. f oscm 500 560 1 1 + =
TB62214AFG/aftg 2012-03-12 20 example application circuits TB62214AFG the values shown in the following figure are typical values. for inpu t conditions, see operating ranges. note: bypass capacitors should be added as necessary. it is recommended to use a single ground plane for the entire board whenever possible, and a grounding method should be considered fo r efficient heat dissipation. in cases where mode setting pins are controlled via swit ches, either pull-down or pu ll-up resistors should be added to them to avoid floating states. for a description of the input va lues, see the function tables. the above application circuit example is presented only as a guide and sh ould be fully evaluated prior to production. also, no intellectual prop erty right is ceded in any way whatsoever in regard to its use. the external components in the above di agram are used to test the electrical characteristics of the device: it is not guaranteed that no system ma lfunction or failure will occur. careful attention should be paid to the layout of the output, v dd (v m ) and gnd traces to avoid short-cir cuits across output pins or to the power supply or ground. if such a short-circuit occurs, the TB62214AFG/aftg may be permanently damaged. also, if the device is installed in a wrong orientation, a high voltage might be applied to components with lower voltage ratings, causing them to be damaged. the TB62214AFG/aftg does not have an overvoltage protecti on circuit. thus, if a voltage exceeding the rated maximum voltage is applied, the TB62214AFG/aftg will be damaged; it should be ensured that it is used within the specified operating conditions. 28 270 pf 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m 3.6 k 0.1 f 100 f 0.51 0.1 f 0.1 f 24 v 0.51 0 v 3.3 v 5 v 0 v 3.3 v 5 v 0 v 3.3 v 5 v 0 v 3.3 v 5 v 0 v 3.3 v 5 v cw/ccw mo_out d_mode_1 d_mode_2 cl k enable reset r s _ a nc out_ a nc gnd out_ a gnd oscm v ref_a v ref_b nc nc v cc v m r s_b nc out_b nc gnd out_b gnd fin(gnd) fin(gnd) 50 k
TB62214AFG/aftg 2012-03-12 21 tb62214aftg the values shown in the following fi gure are typical values. for input co nditions, see the operating ranges. note: bypass capacitors should be added as necessary. it is recommended to use a single ground plane for the entire board whenever possible, and a grounding method should be considered fo r efficient heat dissipation. in cases where mode setting pins are controlled via swit ches, either pull-down or pu ll-up resistors should be added to them to avoid floating states. for a description of the input va lues, see the function tables. the above application circuit example is presented only as a guide and sh ould be fully evaluated prior to production. also, no intellectual prop erty right is ceded in any way whatsoever in regard to its use. the external components in the above di agram are used to test the electrical characteristics of the device: it is not guaranteed that no system ma lfunction or failure will occur. careful attention should be paid to the layout of the output, v dd (v m ) and gnd traces to avoid short-cir cuits across output pins or to the power supply or ground. if such a short-circuit occurs, the TB62214AFG/aftg may be permanently damaged. also, if the device is installed in a wrong orientation, a high voltage might be applied to components with lower voltage ratings, causing them to be damaged. the TB62214AFG/aftg does not have an overvoltage protec tion circuit. thus, if a voltage exceeding the rated maximum voltage is applied, the TB62214AFG/aftg will be damaged; it should be ensured that it is used within the specified operating conditions. nc nc v cc v m r s _ b1 nc nc r s _ b2 nc out_b out_b nc 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 out_b1 gnd nc nc gnd gnd gnd nc nc 37 38 39 40 41 42 43 44 45 46 47 48 oscm v ref_a v ref _b gnd cw/ccw mo_out d_mode_1 d_mode_2 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 cl k enable reset nc r s_a1 nc out_a1 gnd r s_a2 nc out_a2 nc out_b2 out_a2 out_a1 m 270 pf 3.6 k 0.1 f 100 f 0.51 0.1 f 0.1 f 24 v 0.51 0 v 0 v 3.3 v 5 v 0 v 3.3 v 5 v 0 v 3.3 v 5 v 0 v 3.3 v 5 v 3.3 v 50 k 5 v
TB62214AFG/aftg 2012-03-12 22 package dimensions weight: 0.79 g (typ.) hsop28-p-0450-0.80
TB62214AFG/aftg 2012-03-12 23 qfn48-p-0707-0.5 unit: mm backside heatsink: 5.4 mm 5.4 mm corner chamfers: c0.5 chamfer radius: 3-r0.2 weight: 0.14 g (typ.) foot pattern example (double-sided board) surface bottom black dots: 0.2-mm through holes pin#1 index mark area
TB62214AFG/aftg 2012-03-12 24 notes on contents block diagrams some of the functional blocks, circ uits, or constants in the block diagram may be omitted or simplified for explanatory purposes. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omi tted for explanatory purposes. timing charts timing charts may be simplified for explanatory purposes. application circuits the application circuits shown in this document are provided for reference pu rposes only. thorough evaluation is required at the mass production design st age. toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. test circuits components in the test circuits are us ed only to obtain and confirm the devi ce characteristics. these components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. ic usage considerations notes on handling of ics (1) the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings.exceeding the rating(s) may cause device breakdown, damage or deterioration, and ma y result in injury by explosion or combustion. (2) use an appropriate power supply fuse to ensure that a large current does not continuously flow in the case of over-current and/or ic failure. the ic will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead to smoke or ignition. to minimize the effects of the flow of a large current in the case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or brea kdown caused by the current resulting from the inrush current at power on or the negative curre nt resulting from the bac k electromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics with built-in protection fu nctions. if the power supply is unstabl e, the protection function may not operate, causing ic breakdow n. ic breakdown may cause in jury, smoke or ignition. (4) do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power consumption may exceed the abs olute maximum rating, and exc eeding the rating(s) may cause device breakdown, damage or deterioration, and may result in injury by expl osion or combustion. in addition, do not use any device that has been inserted incorrectly. (5) please take extra care when selecting ex ternal components (such as power amps and regulator s) or external devices (for instance, speakers). when large amounts of leak cu rrent occurs from capacitors, the dc output level may increase. if the output is connected to devices such as sp eakers with low resist voltage , overcurrent or ic failure may cause smoke or ignition. (the ove r-current may cause smoke or ignition from the ic itself.) in particular, please pay attention when using a bridge tied load (btl) connection-type ic that inputs output dc voltage to a speaker directly.
TB62214AFG/aftg 2012-03-12 25 points to remember on handling of ics over current protection circuit over current protection circuits (referred to as current limiter circuits) do not necessarily protect ics under all circumstances. if the over current protection circuits operate against the over current, clear the over current status immediately. depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the over current protection circuit to not operate properly or ic breakdown before opera tion. in addition, depending on the method of use and usage conditions, if over current continues to flow for a long time after operation, the ic may generate heat resulting in breakdown. thermal shutdown circuit thermal shutdown circuits do not necessarily protect ics und er all circumstances. if the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properl y or ic breakdown before operation. heat radiation design in using an ic with large current flow such as power amp, re gulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction te mperature (tj) at any time and condition. these ics generate heat even during normal use. an inadequate ic heat radiation design can lead to decrease in ic life, deterioration of ic characteristics or ic breakdown. in addition, please design the device taking into cons iderate the effect of ic heat radiation with peripheral components. back-emf when a motor rotates in the reverse direction, stops or sl ows down abruptly, a current flow back to the motor?s power supply due to the effect of back-emf. if the current sink capabi lity of the power supply is small, the device?s motor power supply and output pins might be exposed to conditions beyond absolute maximum ratings. to avoid this problem, take the effect of back-emf into consideration in system design.
TB62214AFG/aftg 2012-03-12 26 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (colle ctively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software and systems (collectively ?product?) without notice. ? this document and any information here in may not be reproduced without prior wr itten permission from toshiba. even with toshiba?s written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product?s quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malf unction or failure of product could cause loss of human life, b odily injury or damage to property, including da ta loss or corruption. before customers us e the product, create designs including the product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and conditions set forth in the ?toshiba semiconductor reliability handbook? and (b) the instructio ns for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determinin g the appropriateness of the use of this product in such des ign or applications; (b) evaluating and determining the applicability of any information c ontained in this document, or in charts, dia grams, programs, algorithms, sample application circuits, or any othe r referenced documents; and (c) validating all operating paramete rs for such designs and applications. toshiba assumes no liability for customers? product design or applications. ? product is intended for use in general electronics application s (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home el ectronics appliances) or for specific applicat ions as expressly stated in this document . product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may caus e loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limit ation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automo biles, trains, ships and other transportation, traffic signalin g equipment, equipment used to control comb ustions or explosions, safety devices, el evators and escalators, devices related to el ectric power, and equipment used in finance-rela ted fields. do not use product for unintend ed use unless specifically permitted in thi s document. ? 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